In-Pipeline Processor Protection against Soft Errors

The shrinking of technology nodes allows higher performance, but susceptibility to soft errors increases. protection has been implemented mainly by lockstep or hardened process techniques, which results in a lower frequency, larger area, and power consumption. We propose technique that only slightly affects the maximal frequency. area consumption increase are comparable with dual architectures. A reaction faults ability recover from them is similar triple modular redundancy novelty lies applying into processor’s pipeline its separation two sections. provides fast detection faults, simple recovery flush pipeline, large prediction unit be unprotected. proactive component automatically scrubs register file prevent fault accumulation. whole scheme can fully at transfer level. present inside RISC-V core RV32IMC instruction set. Simulations confirm handle injected faults. Synthesis shows lowers maximum frequency about 3.9%. increased 108% 119%.